High Level Abstractions and Automatic Optimization Techniques for the Programming of Irregular Algorithms

Prof. David Padua

Department of Computer Science

University of Illinois at Urbana-Champaign


High-performing irregular algorithms are typically implemented using simple operations and conventional control structures. In addition, due to today’s compilers inability to manipulate these implementations, program tuning must usually be done by hand. Better notations and automatic optimization would help improve programmer productivity, portability, and maintainability. This talk will review high-level notation proposals for the description of irregular algorithms, as well as compiler and autotuning techniques for the optimization of these algorithms. A short discussion of open research problems and necessary conditions for adoption of these more advanced notations and strategies will conclude the presentation.



About the Speaker


David Padua is the Donald Biggar Willet Professor of engineering at the University of Illinois, where he has been a faculty member since 1985. His has conducted research in parallel computing, autotuning, and compilers and has published more than 170 papers in these areas. He has participated in the organization of more than 70 conferences and workshops and served on the editorial board of ACM TOPLAS, JPDC, IEEE TPDS, and IJPP and as Editor in Chief of the Encyclopedia of Parallel Computing (Springer‐Verlag). He is a fellow of the IEEE and the ACM and the recipient of the 2015 IEEE Computer Society Harry H. Goode Award.





Memory Wants To Be Free

Dr. Paolo Faraboschi

HPE


The data deluge caused by proliferation of connected data sources is causing an unprecedented imbalance in the ability of our IT infrastructure to access and mine that data. While it is relatively easier to provision compute resource, it is much more challenging to provision the necessary data resources to feed them. This is true across the entire memory and storage hierarchy which is going through a profound transformation. This talk discusses why we need a new approach to architect the memory and storage systems, what the motivating use cases are, what the obstacles are, and what we can do to address them. It then introduces the technology behind the recently announced Gen-Z consortium (www.genzconsortium.org), an open systems interconnect designed to provide memory semantic access to data and devices via direct-attached, switched, or fabric topologies.


About the Speaker


Paolo Faraboschi is a Fellow and VP at Hewlett Packard Enterprise. His interests are at the intersection of system architecture and software. He is currently working on The Machine project, researching how we can build better memory-driven computing systems. From 2010 to 2104, he worked on low-energy servers and HP project Moonshot. From 2004 to 2009, at HP Labs in Barcelona, he led a research activity on scalable system-level simulation and modelling. From 1995 to 2003, at HP Labs Cambridge, he was the principal architect of the Lx/ST200 family of VLIW cores, widely used in video SoCs and HP's printers. Paolo is an IEEE Fellow and an active member of the computer architecture community. He is an author on 30 patents over 100 publications and the book “Embedded Computing: a VLIW approach”. Before joining HP in 1994, he received a Ph.D. in EECS from the University of Genoa, Italy.