Workshop on Large-Scale Parallel Processing: Practice and Experience
to be held in conjunction with the
IEEE International Parallel and Distributed Processing Symposium
May 29rd - June 2th, 2017
Preliminary Schedule and Keynote Information Available Soon!
The Large-Scale Parallel Processing: Practice and Experience workshop is a forum that focuses on best-practice approaches to the design and utilization of computer systems that scale to thousands of processing elements and beyond. Large-scale systems, referred to by some as Extreme-scale or Ultra-scale, have many important research aspects that need detailed examination in order for their effective design, deployment, and utilization to take place. These include, but are not limited to, handling the substantial increase in per-chip core count, heterogeneity and specialized processor and intra-node architectures, complex communication and memory hierarchies, and communication and synchronization mechanisms. The workshop aims to bring together researchers and practitioners that have experience designing, building, and using such systems for a dynamic exchange of ideas. The goal is to span topics that range from hardware through the software and application stacks.
Of particular interest are papers that identify and analyze novel ideas rather than providing incremental advances in the following areas:
Large-scale systems: exploiting parallelism at large-scale, the coordination of large numbers of processing elements, synchronization and communication at large-scale, programming models and productivity
Novel architectures and experimental systems : the design of novel systems, the use emerging technologies such as Non-Volatile Memory, Silicon Photonics, application-specific accelerators and future trends.
Monitoring, Analysis, and Modeling: tools and techniques for gathering performance, power, thermal, reliability, and other data from existing large scale systems, analyzing such data offline or in real time for system tuning, and modeling of similar factors in projected system installations.
Multi-core: utilization of increased parallelism on a single chip, the possible integration of these into large-scale systems, and dealing with the resulting hierarchical connectivity.
Energy Management: Techniques, strategies, and experiences relating to the energy management and optimization of large-scale systems.
Applications: novel algorithmic and application methods, experiences in the design and use of applications that scale to large-scales, overcoming of limitations, performance analysis and insights gained.
Results of both theoretical and practical significance will be considered, as well as work that has demonstrated impact at small-scale that will also affect large-scale systems. Work may involve algorithms, languages, various types of models, or hardware. A list of papers presented at previous LSPP workshops can be found here.
Papers should not exceed ten single-space pages (including figures, tables and references) using a 12-point on 8½x11-inch pages. Submissions in PostScript or PDF should be made using EasyChair. Informal enquiries can be made to Kevin Barker. Submissions will be judged on correctness, originality, technical strength, significance, presentation quality and appropriateness. Submitted papers should not have appeared in or under consideration for another venue.
|Submission opens:||November 30th 2016|
|Papers due:||January 16th 2017|
|Notification of acceptance:||Februrary 17th 2017|
|Camera-Ready Papers due:||February 27th 2017|
|Kevin J. Barker||Pacific Northwest National Laboratory|
|Eric van Hensbergen||ARM|
|Darren J. Kerbyson||Pacific Northwest National Laboratory|
|Ram Rajamony||IBM Austin Research Lab|
|H.J. Siegel||Colorado State University|
|Charles Weems||University of Massachusetts|
Workshop General Chair and point of contact: Kevin J. Barker