Welcome to the Workshop on Modeling & Simulation of Exascale Systems & Applications Series
Workshop Description:
Multiple significant technical challenges punctuate the path to Exascale. Millions of threads of parallelism need be tractable and manageable. New algorithms and programming models may be required that can utilize these extreme levels of parallelism and can be efficiently mapped to system resources.
Power efficiency is emerging as the overarching design constraint. The cost of data movement in both power and performance is larger than the cost of the arithmetic and may be one order of magnitude or more, higher on the way to Exascale using current technologies. High-speed interconnect networks and communication mechanisms need to cope with the realities of size and complexity within a limited power envelope, which may require streamlined lower-dimensionality topologies. The increase in the depth of memory hierarchies, including additional layers in the I/O and storage subsystem design through the likely addition of power efficient non-volatile memories, leads to increased distances for data to travel as well as increased programming complexity.
An important issue to overcome with Exascale is the intrinsic limitation in reliability given the size and complexity of the systems that will require increased resiliency. There is no one size fits all solution and the challenge ahead is dealing with the combined reliability & power & performance requirements and their tradeoffs at all levels of the stack between the hardware and application.
In a nutshell, at this juncture in time when the HPC community led by DOE is embarking on the path to Exascale, the issue of optimal co-design of Exascale applications and systems takes center stage.
For these reasons, this workshop series was created in 2012. These workshops provides a fertile ground for discussions and brainstorming on how to tackle the issues that the Path to Exascale provides. For access to past and current workshops, please click on the left banner.