Future HPC systems: the Challenges of Power-Constrained Performance

June 25th

To be held in conjunction with

International Conference on Supercomputing

In the past, the computational requirements of important scientific applications have often driven innovations in high performance computing. Presently major changes in computer architectures are taking place that are often driven by consumer electronics. In addition as systems continue to scale in size, we expect that power consumption will become a major concern for future generation supercomputers. Current systems consume more than a Megawatt per Petaflop. Achieving Exascale levels of computation - a 100x improvement in performance from today - will be significantly constrained if power requirements were to similarly scale. The optimization of power and energy at all levels, from application to system software and to hardware at both processor and system scales, is required.

The challenges ahead are many-fold. Increasing parallelism, memory systems, interconnection networks, storage and uncertainties in programming models all add to the complexities. The recent trend with integrating accelerators in large-scale systems provides additional challenges in marshaling the increased parallelism and data movements. More rapid realization of energy savings will require significant increases in measurement resolution and optimization techniques. The interplay between performance, power, and reliability also leads to complex trade-offs.

This workshop aims at reviewing the latest development of HPC systems, that in the near future may evolve in directions substantially different from today's paradigms. We are interested in assesing their potential impact on scientific computing, and in state-of-the-art tools and techniques for measuring and optimizing performance as well as power. We will also discuss new hardware capabilities that may become crucial in the near future for accurate monitoring and optimization of performance and power.

The workshop will comprise of invited speakers that will cover recent advances in the following areas:

- Analysis of future technologies that will provide improved performance and energy efficiencies

- Techniques that enable power and/or Energy optimizations

- Tools for analyzing Performance and Power

- Experiences from current large-scale science and engineering applications and HPC systems

Workshop Schedule

8:30      Server architectures for energy-efficient computing, Jose Moreira, IBM Watson, USA

9:05      Overall System Design of the K computer, FX10 and beyond -- Current Progress and Issues for the Next Step , Shinji Sumimoto, Fujitsu, Japan

9:40      Top-down view on exascale architecture , Andrey Slepuhin, T-Platforms

10:15      Break

10:50      EURORA: a European architecture toward Exascale , Carlo Cavazzoni, CINECA, Italy

11:25      SpiNNaker: a low-power, low-latency approach to super-computing for Neural network applications , David Lester, U. Manchester, UK

12:00      Janus2: An FPGA-based Supercomputer for Spin Glass Simulations , Andrea Maiorano, U. Roma, Italy

12:35      Lunch

14:00      On the scalability of the cluster-booster concept , Nobert Eicker, JSC, Germany

15:00      The Mont-Blanc approach towards Exascale , Alex Ramirez, BSC, Spain

15:30      Break

16:20      Designing for Throughput: An alternate many core runtime architecture , Costin Iancu, LBNL, USA

16:55      Using Application Information to Save Energy: The Energy Template Approach , Darren J. Kerbyson, PNNL, USA

17:30      Closing Remarks

Workshop Organizers

Sanzio Bassini CINECA, Italy
Adolfy Hoisie Pacific Northwest National Laboratory, USA
Darren J. Kerbyson Pacific Northwest National Laboratory, USA
Dirk Pleiter Jülich Supercomputing Centre and University of Regensburg, Germany
Sebastiano Fabio Schifano University of Ferrara, Italy