Third International Workshop on

Domain-Specific Languages and High-Level Frameworks for High Performance Computing

November 18, 2013

Full-day Workshop at

The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC) 2013

Denver, Colorado, USA

| Home | Advance Program |

Please provide workshop feedback here

Workshop Description

Multi-level heterogeneous parallelism and deep memory hierarchies in current and emerging computer systems make their programming for high-performance applications very difficult. The task is made more challenging by the changing landscape of system architecture mandated by power and micro-architecture considerations. Domain-specific languages (DSLs) and high-level frameworks (HLFs) provide convenient abstractions, shielding application developers from much of the complexity and variability of explicitly programming in standard programming languages like C/C++/Fortran. Effective design of such abstractions for the high-performance computing context requires close interaction between researchers developing such languages and frameworks and domain experts with a deep understanding of the problem to be solved.

While a number of other venues exist that address domain-specific languages and high-level programming abstractions, none of them focus on the challenges to performance optimization and implementation on parallel systems. This workshop seeks to bring together developers and users of DSLs and HLFs to identify challenges and discuss solution approaches for their effective implementation and use on a variety of platforms, including massively parallel systems.

We solicit submissions on all aspects relating to domain-specific languages and high-level frameworks for the HPC context, including, but not limited to, the design, implementation, evaluation, or use of:

Submission Guidelines

Extended abstracts should be two or more pages in pdf format but less than 10 pages (all inclusive) and follow IEEE conference formatting guidelines. In addition to new ideas, experience stories, challenges faced, and overview of prior work are encouraged.

At least one of the authors of each accepted submission is expected to attend and present at the workshop. The final manuscripts of papers will be made available in IEEExplore as part of SC13 proceedings.

Submissions can be made online at easychair.

Important Dates

Submission deadline : 1 Sep 2013 27 Sep 2013
Author notification : 1 Oct 2013 11 Oct 2013
WOLFHPC workshop : 18 Nov 2013

Keynote Talks

What Parallel HLLs Need

Keynote Speaker: Laxmikant Kale
University of Illinois, Urbana-Champaign

Abstract: Higher levels of abstractions that increase productivity can be designed by specializing them in specific ways. Domain-specific languages, interaction pattern specific languages, APGAS languages, or high-level frameworks leverage their own specializations to raise abstraction levels and increase productivity. In this talk, I will present some common support that all such higher level abstractions need, and the need to encapsulate that support in a single common substrate. In particular, the support includes automatic resource management, and other runtime adaptation support, including that for tolerating component failures or handling power/energy issues. Further, I will explore the need to interoperate and coordinate across multiple such paradigms, so that one can construct multi-paradigm applications with ease. I will illustrate the talk with my group's experience in designing multiple interaction-pattern-specific HLLs, and on interoperability among them as well with traditional message-passing paradigm of MPI.

Adjusting to Exascale Computing — Do DSLs Stand a Chance?

Keynote Speaker: Patrick McCormick
Los Alamos National Laboratory

Abstract: The current MPI+Fortran ecosystem has sustained HPC application software development for the past decade, but was architected for coarse-grained concurrency and bulk-synchronous algorithms. The trends in computer architecture have turned the model for achieving good performance upside-down, and will require rethinking algorithms and our entire programming environment. There are already promising avenues of exploration underway to mitigate these effects. Future hardware constraints on bandwidth and memory capacity, together with exponential growth in explicit on-chip parallelism will likely require a mass migration to new algorithms and software architecture that is as broad and disruptive as the migration from vector to parallel computing systems that occurred 15 years ago. The challenge is to efficiently express massive concurrency, parallelism, and hierarchical data locality without subjecting the programmer to overwhelming complexity. This talk will give a glimpse of DOE's program to overcome these obstacles and discuss the challenges we face in making domain-specific languages a successful part of the solution.

Workshop Organization

Organizing Committee

Sriram Krishnamoorthy, Pacific Northwest National Laboratory
J. (Ram) Ramanujam, Louisiana State University
P. (Saday) Sadayappan, The Ohio State University

Program Committee

Muthu Baskaran, Reservoir Labs
Uday Bondhugula, Indian Institute of Science
George Bosilca, University of Tennessee, Knoxville
James Dinan, Intel
Jeff Hammond, Argonne National Lab
Paul H.J. Kelly, Imperial College London
Rishi Khan, ET International
Milind Kulkarni, Purdue University
Wenjing Ma, Institute of Software, Chinese Academy of Sciences
Kamesh Madduri, Penn State University
Xipeng Shen, College of William & Mary
Didem Unat, Lawrence Berkeley National Lab


Please contact the program chairs at: wolfhpc13@easychair.org