The Challenges of Achieving Power and Performance Efficiences for HPC: From Design-space Exploration to Dynamic Optimization June 10th 2014 To be held in conjunction with International Conference on Supercomputing

Sudhakar Yalamanchili

Georgia Institute of Technology

With the end of Dennard scaling and as industry moves to increasingly small feature sizes, performance scaling will become increasingly dominated by the physics of the computing environment. There are fundamental trade-offs to be made at the microarchitectural level between performance, energy/power, and reliability. New efforts are emerging that are targeting understanding, characterizing, and collaboratively managing the multi-physics and multi-scale (nanoseconds to milliseconds) transient interactions between the delivery, dissipation, and removal (cooling) of energy and their impact on system level performance. In particular, these tradeoffs are driven by application workloads. This talk will describe how interacting physical phenomena can affect microarchitecture-level tradeoffs and lead to operational principles for energy-efficient multicore performance scaling. Several examples are presented of the application of these principles to managing tradeoffs between performance, energy, and reliability on commodity and future heterogeneous processors.

With Exascale systems on the horizon, we have ushered in an era with power and energy consumption as the primary concerns for scalable computing. To achieve a viable Exaflop high performance computing capability, revolutionary methods are required with a stronger integration among hardware features, system software and applications. Equally important are the capabilities for fine-grained spatial and temporal measurement and control to facilitate these layers for energy efficient computing across all layers. This workshop seeks to address the important energy efficiency aspects in the HPC community. Emphasis is given to the application’s view related to significant energy efficiency improvements and to the required hardware/software stack that must include necessary power and performance measurement and analysis harnesses. This workshop aims to bring together researchers from different communities working on challenging problems in this area for a dynamic exchange of ideas.

Current tools are often limited by hardware capabilities and their lack of information about the characteristics of a given workload/application. In the same manner, hardware techniques, like dynamic voltage frequency scaling, are often limited by their granularity (very coarse power management) or by their scope (a very limited system view). More rapid realization of energy savings will require significant increases in measurement resolution and optimization techniques. Moreover, the interplay between performance, power and reliability add another layer of complexity to this already difficult group of challenges.

Areas of particular interest are research topics that identify and analyze novel ideas rather than providing incremental advances in the following areas:

- Tools for analyzing power and energy with different granularities and scope from hardware (e.g. component, core, node, rack, system) or software views (e.g. threads, tasks, processes, etc) or both

- Techniques that enable Power and Energy optimizations at different scale levels for HPC systems

- Integration of power aware techniques in applications and throughout the software stack of HPC systems

- Dynamic power optimization tools and techniques

- Methods for data movement reduction within a system

- Characterization of current state-of-the-art HPC system and applications in terms of Power

The workshop will comprise of invited experts that will cover recent advances in the above areas

Workshop Organizers

	Adolfy Hoisie	Pacific Northwest National Laboratory, USA
	Darren J. Kerbyson	Pacific Northwest National Laboratory, USA

Workshop point of contact: Darren J. Kerbyson