MTAAP'08
Workshop on Multithreaded Architectures and Applications

Held in Conjunction With
International Parallel and Distributed Processing Symposium (IPDPS 2008)

Miami, April 18, 2008

Workshop Organization

Chairs

Luiz DeRose (Cray)
Jarek Nieplocha (PNNL)

Program Committee

David Bader (Georgia Tech)
Jonathan Berry (Sandia National Laboratory)
Barbara Chapman (U. Houston)

Daniel Chavarria (Pacific Northwest National Laboratory)

Hubertus Franke (IBM)
Guang Gao (U. Delaware)
Bruce Hendrickson (Sandia National Laboratory)
Larry Kaplan (Cray)

Peter Kogge (Notre Dame)
Andres Marquez (Pacific Northwest National Laboratory)
Michael Merrill (DoD)

Jose Moreira (IBM)
P. Sadyappan (Ohio State)
Mateo Valero (Universitat Politècnica de Catalunya)
Jeff Vetter (Oak Ridge National Laboratory, Georgia Tech)

Hans Zima (NASA Jet Propulsion Laboratory)

This is a continuation of the succesful MTAAP'07 Workshop held last year in Long Beach, CA.

Theme

Multithreading (MT) programming and execution models are starting to permeate the high-end and mainstream computing scene. This trend is driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures that fit this profileare Cray's XMT, IBM Cyclops, and several SMT processors from Sun (UltraSparc T1&T2), IBM (Power5+, Power6), Intel. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement. This workshop intends to identify applications that are amenable to MT and the MT programming and execution models as well as the underlying architectures on which they can thrive. The workshop seeks to explore programming frameworks in the form of MT languages and libraries, compilers, analysis and debugging tools to increase the programming productivity.

Topics of Interest

Topics of interest are guided by their application impact and include but are not limited to following topics:

• Multithreaded Performance Metrics and Evaluations
• Multithreaded Architectures
• Multithreaded Programming Framework
• Innovative applications for MT architectures
• Compilation and Optimization for MT architectures
• Multithreaded Libraries and runtime systems
• Multithreaded Performance Analysis and Debugging Tools

Results of both theoretical and practical significance will be considered.

Preliminary Program

I. 9:00-9:10am:  Welcome Message 

II. 9:10-10am: Keynote Talk: Jonathan Berry (Sandia) (slides)

10:00-10:30am Break

III. 10:30-12:00pm: Performance

• Sheng Li, Shannon Kuntz, Peter Kogge, Jay Brockman, Memory Model Effects on Application Performance for a Lightweight Multithreaded Architecture
• Nikos Anastopoulos, Nectarios Koziris, Facilitating Efficient Synchronization of Asymmetric Threads on Hyper-Threaded Processors
• Daniel Chavarria, Andres Marquez, Jarek Nieplocha, Kristyn Maschhoff,  Early Experience with Out-of-Core Applications on the Cray XMT

12:00-1:00pm Lunch Break

IV. 1:00-3:00pm  Algorithms and Programming Models

• Gregorio Quintana-Ortí, Enrique Quintana Orti, Ernie Chan, Field Van Zee, Robert van de Geijn, Design of Scalable Dense Linear Algebra Libraries for Multithreaded Architectures: the LU Factorization
• Kyle Wheeler, Richard Murphy, Douglas Thain, Qthreads: An API for Programming with Millions of Lightweight Threads
• Bo Hong, A Lock-free Multi-threaded Algorithm for the Maximum Flow Problem
• Jonathan Byrd, Stephen Jarvis, Reducing the Run-time of MCMC Programs by Multithreading on SMP Architectures

3:00-3:30pm Break

V. 3:30-5:00pm Architecture

• Sevin Fide, Architecture Optimizations for Synchronization and Communication on Chip Multiprocessors
• Satoshi Yamada, Shigeru Kusakabe, Effect of Context Aware Scheduler on TLB
• Hongzhou Chen, Lingdi Ping, Xuezeng Pan, Kuijun Lu, A Dissipative Resource Distribution Policy for SMT Processors
  

Proceedings

The proceedings of this workshop are included in the proceedings of other IPDPS 2008 workshops by the IEEE Computer Society Press.

Paper Submissions 

Submitted manuscripts may not exceed 20 single-spaced pages using a 12-point font on 8½×11-inch pages, everything included (figures, tables, references, etc.). Manuscripts must be submitted electronically and in either PostScript or PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal.

MTAAP submissions are being handled by EDAS system. To submit a paper, please use the following link https://edas.info/newPaper.php?c=5715&submit=0& and follow the instructions.

Important Dates

Papers due:	23 December 2007 (extended)
PC reviews due:	1 January 2008
Notification of acceptance:	5 January 2008
Camera-ready due:	20 January 2008

Additional Information

E-mail Contact

For more information on MTAAP 2008 or if you have any questions please contact the workshop organizers at the e-mail address listed at the bottom of this page.