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Mobirise

9th Workshop on Irregular Applications: Architectures and Algorithms

November 18, 2019
Colorado Convention Center, Denver, CO
In conjunction with SC19
Sponsored by IEEE TCHPC

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Program

Time Event
9:00 - 9:10Welcome and Introduction
Antonino Tumeo, John Feo, Vito Giovanni Castellana
9:10 - 10:00Keynote 1  - Chair: Vito Giovanni Castellana (PNNL)

Khronos SYCL: Heterogeneous Programming with Modern C++ and Machine Learning
Micheal Wong (Codeplay)
10:00 - 10:30Coffee Break
10:30 - 11:30Session 1: Distributed Systems and Irregular Applications - Chair: Ryan Friese (PNNL)

Conveyors for Streaming Many-To-Many Communication
Maley, DeVinney

Extending a Work-Stealing Framework with Priorities and Weights
Nakashima, Yoritaka, Yasugi, Hiraishi, Umatani

RDMA vs. RPC for Implementing Distributed Data Structures (short)
Brock, Chen, Yan, Owens, Buluç, Yelick
11:30 - 12:30Session 2: Mixed Precision and new memory hierarchies for Irregular Applications - Chair: Sayan Ghosh (PNNL)

A Mixed Precision Multicolor Point-Implicit Solver for Unstructured Grids on GPUs
Walden, Nielsen, Diskin, Zubair

Mixed-Precision Tomographic Reconstructor Computations on Hardware Accelerators
Doucet, Ltaief, Gratadour, Keyes

Metall: A Persistent Memory Allocator Enabling Graph Processing (short)
Iwabuchi, Lebanoff, Gokhale, Pearce
12:30 - 14:00Lunch break (on your own)
14:00 - 14:50Keynote 2 - Chair: Marco Minutoli (PNNL)

Sparse Linear Algebra in Facebook's Deep Learning Models
Jongsoo Park (Facebook)
14:50 - 15:00Session 3: Dealing with Irregular Algorithms - Chair: Vinay Amatya (PNNL)

iPregel: Strategies to Deal with an Extreme Form of Irregularity in Vertex-Centric Graph Processing (short)
Capelli, Brown, Bull
15:00 - 15:30Coffee Break
15:30 - 15:55Session 3 (continued): Dealing with Irregular Algorithms - Chair: Vinay Amatya (PNNL)

Stretching Jacobi: A Two-Stage Pivoting Approach for Block-Based Factorization
Thuerck
15:55 - 16:40Session 4: Hardware evaluation and mechanisms for Irregular Applications - Chair: Tania Lorido Botran (PNNL)

A Hardware Prefetching Mechanism for Vector Gather Instructions
Takayashiki, Sato, Komatsu, Kobayashi

Performance Impact of Memory Channels on Sparse and Irregular Algorithms (short)
Green, Fox, Young, Shirako, Bader

Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications (short)
Kashimata, Kitamura, Kimura, Kasahara
16:40 - 17:30Debate - Moderator: Flavio Vella (Free University of Bozen)

Proposition: "Programming abstractions can greatly simplify the expression of
complex workflows of data analytic applications, but make it difficult to customize
source code for heterogeneous computer systems.
Unfortunately, it is an either or situation --- easy expression or fast performance"

Panelists: Nesreen Ahmed (Intel), Jonathan Beard (ARM), 
Tyler Sorensen (Princeton University), Ana Lucia Verbanescu (University of Amsterdam)