14th Workshop on Irregular Applications: Architectures and Algorithms

November 18, 2024
Atlanta, GA
In conjunction with SC24


Call for Papers

Emerging data-intensive, supercomputing applications are moving towards a convergence of scientific simulations, data analytics, and learning algorithms. Many of the components of these applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. In processing massive sets of unstructured data, the components often execute many irregular, fine-grain accesses and synchronization events. Since current high-performance programming models, runtimes, and architectures rely on regular task graphs, bulk synchronous communications and high temporal and spatial data locality to reduce operational latencies, it is difficult to express irregular applications in current HPC programming models and scale performance on current supercomputing machines. Development of improved programming and execution models that address the issues of irregular applications is critical to solving the data challenges in large-scale science and data analysis.
This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system architecture, network, languages and libraries, runtimes, compilers, algorithms, and performance studies. Topics of interest, of both theoretical and practical significance, include but are not limited to:
- Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors 
- Network architectures and interconnects including high-radix and optical networks 
- Novel memory architectures and designs (including processors-in memory) 
- Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) 
- Modeling, simulation, and evaluation of novel architectures with irregular workloads 
- Languages and programming models for irregular workloads
- Library and runtime support for irregular workloads
- Compiler and analysis techniques for irregular workloads
- Innovative algorithmic techniques for irregular workloads
- Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
- Impact of irregularity on machine learning approaches
- Parallelization techniques and data structures for irregular workloads
- Data structures combining regular and irregular computations (e.g., attributed graphs)
- Approaches for managing massive unstructured datasets (including streaming data) 
- High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning)
- Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads
The workshop welcomes regular paper submissions, papers describing work-in-progress or incomplete but sound, as well as innovative ideas related to the workshop theme. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.

Important Dates

  • Abstract Submission: July 26, 2024 (AoE) 
  • Position or Regular Paper Submission: August 2, 2024 (AoE) 
  • Notification: September 8, 2024
  • Camera-ready: September 30, 2024
  • Workshop: November 18, 2024


Submission site: TBD

Submitted manuscripts may not exceed eight (8) pages in length for regular papers (excluding references) and four (4) pages for position papers (including references).
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.

The templates are available at:

The proceedings of the workshop will be published in the IEEE Digital Library in cooperation with IEEE Computer Society.

Artifact Description & Evaluation

This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE:

Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. Note that differently from the main conference, this additional page is voluntary (not mandatory - i.e., if a paper has no computational results, do not attach it) for the workshop, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. 

Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared publicly (for example, through the CK - Collective Knowledge - format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. 

For any additional question on the AD and the AE please contact the Artifact Evaluation Chair, Biagio Cosenza, at

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